Flip-flops are widely used in integrated circuits, such as in microprocessors and other digital circuits to temporarily store data. A flip-flop stores data by sampling an input data signal with a clock signal at a particular instant of time, typically at an edge of the clock. The output of the flip-flop is sensitive to the input data signal at the clock edge. At all other times, the output does not respond to changes in the input data signal.
A flip-flop can be realized in a variety of ways as understood by a person skilled in the art. A typical way of realizing a flip-flop is to use two series connected latches called a master and a slave as illustrated in FIG. 8. In the illustrated example, the master latch is transparent to a low (0) clock signal level while the slave is transparent to a high (1) clock signal, making the output of the flip-flop sensitive only to 0 to 1 transition of the clock. However, such master-slave flip-flops present several shortcomings. For example, in order to change the output of the master-slave flip-flop, a signal propagates through both the master and the slave stages. The resulting delay poses limitations in high speed circuits. Further, the data values in the master and the slave stages can be susceptible to ionizing radiation. Types of ionizing radiation may include alpha particles and cosmic neutrons. These particles can generate a large number of electron hole pairs, which may be collected by the storage nodes and result in a data upset, which is known as a soft error (SE). This is particularly true for nanoscaled circuits where the charge representing a data state on a storage node is very small due to low node capacitance and supply voltage.
The SE problem is addressed by using SE immune latches, such as the Dual Interlocked Cell (DICE) latch, for the master and slave stages. For example, referring to FIG. 9, a schematic diagram of an SE immune flip-flop having master slave stages is illustrated. However, this type of flip-flop has a large number of transistors, which can cause significant delay, an increase in area, and power penalties. In addition, the flip-flop increases the clock load and hence the clock power consumption. As a consequence, this type of flip-flop is not suitable for high speed or low power applications.
Due to the growing need for technology scaling and the corresponding susceptibility to radiation induced soft error, it would be advantageous to provide soft error robust flip flops. Further, it is desirable to improve the flip flop circuit immunity against soft error while limiting the number of extra transistors. Reducing the number of transistors allows the flip-flops to occupy less space and permits higher cell density. As well, fewer transistors reduce delay, and allow for more efficient power usage such that the flip flops may be suitable for high speed or low power applications.